1. Field of the Invention
The invention relates to a resistance ladder, a D-A converter based on the resistance ladder, and an A-D converter using the D-A converter.
2. Description of the Prior Art
An A-D converter which converts an analog voltage into a digital value requires a reference voltage which is to be compared with a to-be-converted object, i.e., the analog voltage. In a typical A-D converter, an analog reference voltage for comparison is generated by a D-A converter using a resistance ladder in which plural resistors are connected in series.
FIG. 1 is a circuit diagram showing the configuration of main portions of a D-A converter of n-bit resolution which uses a conventional resistance ladder. This prior art example is a D-A converter of 4-bit resolution. In the figure, 1 designates a positive analog voltage source (VREF), and 2 designates a negative analog voltage source (AVSS). A resistance ladder 3 is connected to the positive and negative analog voltage sources 1 and 2. The resistance ladder 3 consists of: a string of resistors 4, 4, . . . in which (2.sup.n -2) [=14] resistors 4 each having a resistance of R are connected in series; a resistor 6 which has a resistance of 3R/2, and through which one end of the string of resistors 4, 4, . . . is connected to the positive analog voltage source 1; and a resistor 5 which has a resistance of R/2, and through which the other end of the string of resistors 4, 4, . . . is connected to the negative analog voltage source 2. The resistance ladder 3 has a total resistance of 16.multidot.R, and divides the potential difference between the positive and negative analog voltage sources 1 and 2 into 2.sup.4 levels. Ladder taps T1 through T16 through which division voltages of 2.sup.4 levels are taken out are connected to the node between the resistor 5 of the resistance ladder 3 and the negative analog voltage source 2, and to the nodes between the other resistors, respectively.
A switching tree 7 comprises a group of switches 70 through 77 which are controlled so as to select one of the ladder taps T1 through T16 of the resistance ladder 3 to obtain an analog output 8. The on/off operations of the group of switches 70 through 77 ace respectively controlled by the levels of digital signals a, a, b, b, c, c, d and d which are supplied from an external control circuit (not shown) through word lines, and which indicate a 4-bit digital value "abcd" by means of positive and negative logic. The switches 70 through 77 are turned on when the digital signal corresponding to the letter assigned to the respective switch in FIG. 1 is "1". In other words, FIG. 1 shows a state that the digital value "abcd" is "1010.sub.2 " or the digital signals a, b, c and d are "1" and the other digital signals are "0".
Table 1 shows the relationship between the digital value "abcd", analog voltages of the analog output 8 in the case where VREF and AVSS are 4 V and 0 V, respectively, and the ladder taps T1 through T16 from which the analog voltages are obtained. As seen also from the table, the ladder taps attain voltages in such a manner that the potential difference between the ladder tap T1 as the lowest tap of the resistance ladder from which the potential of AVSS is obtained, and the ladder tap T2 is 0.125 V, the potential difference between VREF and the ladder tap T16 is 0.375 V, and the potential difference between each adjacent two of the other ladder taps T2 through T15 are 0.25 V. In other words, voltages obtained by dividing the potential difference between VREF and AVSS into 2.sup.4 [=16] levels are taken through the ladder taps T1 through T16, respectively.
FIG. 2 shows a sequential approximation type A-D converter of 4-bit resolution which is disclosed in, for example, Japanese Patent Application Laid-Open No. 54-151368 (1979) (U.S. application Nos. 879,646, 968,329), and which uses the D-A converter of FIG. 1. In the figure, 9 designates a D-A converter of 4-bit resolution having the configuration of FIG. 1. The D-A converter 9 supplies an analog voltage of a 4-bit digital value which is one of the analog voltages obtained from the ladder taps T1 through T16 listed in Table 1, to a comparator 16 as a reference voltage to be compared with an analog input (AIN) 25 supplied from outside. A 4-bit control circuit 10 generates digital signals a, a, b, . . . , d which correspond to the 4-bit digital value, and supplies the digital signals to the D-A converter 9 through word lines. Furthermore, the 4-bit control circuit 10 determines the 4-bit digital value on the basis of a comparison result signal 20 outputted from the comparator 16 which compares the analog input 25 with the analog output 8 of the D-A converter 9.
Next, a digital conversion conducted by the thus configured A-D converter in the case where the analog input 25 is 1.3 V will be described.
First, a digital signal corresponding to a digital value "1000.sub.2 " in which the highest-order bit "a" of the digital value "abcd" is set to be "1" is supplied to the D-A converter 9 in order to output the comparison reference voltage therefrom. The D-A converter 9 then supplies a voltage: EQU (VREF/2)-(VREF/32) [V](=1.875 V)
to the comparator 16. The comparator 16 compares the analog output 8 of the D-A converter 9 with the analog input (AIN) 25 as follows: EQU [(VREF/2)-(VREF/32)]:AIN
i.e., EQU 1.875 V:1.3 V
Since AIN is lower, the 4-bit control circuit 10 determines the digital value of the bit "a" to be "0" in accordance with the comparison result signal 20.
Then, a digital signal corresponding to a digital value "0100.sub.2 " in which the bit "b" is set to be "1" is supplied to the D-A converter 9 which in turn supplies a voltage: EQU (VREF/4)-(VREF/32)[V](=0.875 V)
to the comparator 16. The comparator 16 compares the analog output 8 of the D-A converter 9 with the analog input (AIN) 25 as follows: EQU [(VREF/4)-(VREF/32)]:AIN
i.e., EQU 0.875 V:1.3 V
Since AIN is higher, the 4-bit control circuit determines the digital value of the bit "b" to be "1"in accordance with the comparison result signal.
Then, a digital signal corresponding to a digital value "0110.sub.2 " in which the bit "c" is set to be "1" is supplied to the D-A converter 9. The D-A converter 9 supplies a voltage: EQU (3.multidot.VREF/8)-(VREF/32)[V](=1.375 V)
to the comparator 16. The comparator 16 compares the analog output 8 of the D-A converter 9 with the analog input (AIN) 25 as follows: EQU [(3.multidot.VREF/8)-(VREF/32)]:AIN
i.e., EQU 1.375 V:1.3 V
Since AIN is lower, the 4-bit control circuit 10 determines the digital value of the bit "c" to be "0" in accordance with the comparison result signal.
Then, a digital signal corresponding to a digital value "0101.sub.2 " in which bit "d" is set to be "1" is supplied to the D-A converter 9 which in turn supplies a voltage: EQU (5.multidot.VREF/16)-(VREF/32)[V](=1.125 V)
to the comparator 16. The comparator 16 compares the analog output 8 of the D-A converter 9 with the analog input (AIN) as follows: EQU [(5.multidot.VREF/16)-(VREF/32)]:AIN
i.e., EQU 1.125 V:1.3 V
Since AIN is higher, the 4-bit control circuit 10 determines the digital value of the bit "d" to be "1" in accordance with the comparison result signal.
As a result of the above-mentioned sequential comparison, the analog voltage 1.3 V of the input AIN is converted into a digital value "0101.sub.2 ".
An A-D converter of 9-bit resolution can conduct an A-D conversion twice the accuracy when the resolution is 8-bit. Likewise, an A-D converter of 10-bit resolution can conduct an A-D conversion twice the accuracy of 9-bit resolution. As the resolution becomes higher, therefore, a value indicated by the resulting digital value more approximates an input analog value.
An A-D converter in which an analog reference voltage for comparison is generated by a D-A converter based on a resistance ladder has an advantage in the excellent linear conversion properties because the D-A converter based on the resistance ladder generates an analog reference voltage by using only resistors and therefore the resulting division voltages are correct as far as the resistors are uniformly irregular.
On the other hand, in the A-D converter of the above type, the D-A converter must generate division voltages of the corresponding number to the resolution of the A-D converter. Therefore, an A-D converter of 8-bit resolution requires at least 2.sup.8 [=256] resistors. Similarly, an A-D converter of 9-bit resolution requires at least 2.sup.9 [=512] resistors, and that of 10-bit resolution requires at least 2.sup.10 [=1024] resistors. That is, when the resolution is improved every one bit, the number of resistors must be doubled. Consequently, the A-D converter is disadvantageous in that the improvement of the resolution inevitably increases the device area and impairs the production yield thereby to increase the production cost of an LSI.
In order to eliminate the drawbacks discussed above, an improved circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 1-97020(1989). In an A-D conversion process conducted by the circuit, two adjacent ladder taps of a resistance ladder string are selected, another resistance ladder string having a resistance which is much higher than that between the above ladder taps is connected to the ladder taps, and the potential across the selected ladder taps is further divided by the resistor string of a higher resistance, thereby improving the resolution of an A-D converter.
Other prior art A-D converters using a D-A converter include a parallel A-D converter, and a serial-parallel A-D converter in which the D-A converter repeats a conversion process every plural bits in a sequence from a high-order bit to the lowest-order bit, and a comparison between an analog output of every plural bits and an analog input to be converted is repeated to conduct a digital conversion.
FIG. 3 is a circuit diagram showing the configuration of a prior art D-A converter which is used in a parallel A-D converter, or a serial-parallel A-D converter to convert a digital value into an analog value per p bits. The illustrated D-A converter of 4-bit resolution conducts an analog conversion per 2 bits. The D-A converter consists of a resistance ladder in which 2.sup.n [=16] resistors are connected in series, (2.sup.p -1) [=3] analog outputs 81, 82 and 83, and 15 selecting switches 701 through 715 which are used for obtaining the (2.sup.p -1) analog outputs 81, 82 and 83 from the resistance ladder. An A-D converter using the D-A converter has (2.sup.p -1) comparators (not shown) which are respectively connected to the analog outputs 81, 82 and 83, and compares an analog voltage input from outside with analog outputs of the D-A converter resulting from the analog conversions per 2 bits from a high-order bit, to convert the analog value into a digital value.
In the case where a resistance ladder having the configuration of FIG. 1 is employed in the above D-A converter, the improvement of the resolution requires an increase of the circuit scale, similar to the foregoing example. When a D-A converter of 6-bit resolution is to be realized in a configuration similar to that of the D-A converter of 4-bit resolution shown in FIG. 3, for example, the resistance ladder must be composed of at least 64 resistors and requires 62 switches.
In the circuit disclosed in Japanese Patent Application Laid-Open No. 1-97020 (1989) (EP Appl. No. 87480013.9), even when the resistors connected between two ladder taps have a very high resistance, the main current passing through the resistance ladder is theoretically shunted, so that the potential difference between the ladder taps to which the group of high resistance resistors is connected is reduced. In this case, the voltage across the ladder taps to which the group of high resistance resistors is connected is not equal to potential differences of the other ladder taps. Therefore, it is substantially impossible to eliminate an error caused by the reduced potential difference.
If the group of high resistance resistors has a resistance as high as 2,000 times the resistance between adjacent ladder taps of a first resistance ladder, an error due to the connection of the group of high resistance resistors can be reduced to an allowable range. However, even when the error can be reduced to an allowable range, when all the resistors are made of the same material, it is apparent that the group of high resistance resistors occupies a considerably large area.
The problem of a large area occupied by the group of high resistance resistors may be solved by using a material of a high resistivity. Theoretically, switches correcting the resistors of the group to the ladder taps may have a resistance. Unless the circuit is designed with due consideration of the resistance of each switch, therefore, it is impossible to correctly divide the potential difference between the reference voltage sources connected to the both ends of the resistance ladder. In order to configure the circuit in due consideration of the resistances of the switches, the switches must exhibit a uniform resistance at any of the ladder taps.
A D-A converter of 4-bit resolution is disclosed in FIGS. 4 and 5 of Japanese Patent Application Laid-Open No. 54-151368(1979) (U.S. application Nos. 879,646, 968,329), and a 12-bit A-D converter to which the D-A converter is applied is disclosed in FIG. 7. In the D-A converter, 3 unit resistors each having a resistance of R, and subsequently 4 resistors each having a resistance of R/4 are connected in series between a positive analog voltage source and a negative analog voltage source, thereby constituting a resistance ladder. Two analog voltages obtained from the group of the 3 resistors and that of the 4 resistors are supplied to non-inverting and inverting inputs of a buffer, respectively, so that an analog output is obtained in accordance with the difference between the two analog voltages.
In the disclosed converter, the resistance ladder is configured by a small number of resistors, and therefore the resistors occupy a small area. Since the number of the resistors is small, however, a total sum of resistances of the resistance ladder is smaller than that of a resistance ladder composed of series resistors. When the impedances of the positive and negative analog voltage sources are not sufficiently low, charging and discharging currents of a capacitance existing in the resistance ladder causes the analog voltage sources to fluctuate in the output level, with the result that the accuracy of the A-D converter is adversely influenced.
Since resistive component of conductors connecting the resistors each other greatly influence the resistance ladder when the whole resistance thereof is low, the resistance ladder should be composed with careful consideration also to the resistive component, which quantity is little, of the conductors.
In an A-D converter of 6-bit resolution using a D-A converter based on a series resistance ladder, there are 64 ladder taps and 64 paths extending between the ladder taps to an analog output through a switching tree. When the continuity of the ladder taps is to be checked, therefore, accuracy at 64 points must be tested while the A-D conversion is conducted.
At the inspection of LSIs before shipment, when an LSI has even a single faulty transistor in the whole circuit, the LSI is selected as a defective one. Generally, an A-D converter, and an LSI loading the A-D converter are subjected also to testing of the conversion accuracy of the A-D converter. If the A-D converter is composed of a resistance ladder, the testing must be conducted by the number corresponding to the resolution of the A-D converter. As the resolution becomes higher, therefore, the number of testing points is increased so that the test time is lengthen, thereby causing the production cost to be increased.